The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a novel trench isolation structure and method used for electrical isolation in semiconductor devices.
As the level of integration of semiconductor devices is gradually increased, isolation areas can be used to partition an active region and field region within a specific device. Isolation areas can be formed by a Shallow Trench Isolation (STI) process, where the STI process is a method of forming a trench in a predetermined region of a semiconductor substrate where the trench is subsequently filled with an oxide layer to form an isolation structure.
As the level of integration of semiconductor devices such as NAND flash memory devices is increased, the area of the active region that helps to determine the characteristics of the device is gradually reduced. Although the STI process is employed to improve electrical isolation, the pitch of the active region and the field region becomes smaller as the integration of the device is increased. Therefore, to ensure uniform electrical characteristics of devices formed using the STI process, the area of the active region must be increased.
However, void formation can occur if the area of the active region is increased without increasing the overall area of the device. This can happen where a gapfill process takes place as the field region becomes progressively smaller. In contrast, if the area of the field region is increased, the area of the active region becomes smaller which may have an adverse effect on the electrical characteristics of the devices being formed in these regions.
A method of manufacturing a semiconductor device and more particularly a flash memory device could be provided where the yield of the device is improved by increasing the area of an active region without increasing the overall area of the device.